The present invention relates generally to integrated circuits, and more particularly to method and apparatus for testing high-speed circuits based on slow-speed signals.
Memory devices are integral to computer systems and many electronic circuits. Continuous improvements in the operating speed and computing power of central processing units (CPUs) enable the operation of an ever-greater variety of applications, many of which require larger and faster memories. Larger memories are characterized by having more memory cells to store more bits of data. And faster memories are possible by using smaller geometry for the memory cells and employing circuitry that ensures proper operation at the higher speed.
The manufacturing process for larger and faster memory devices is very challenging due to the complicated process to fabricate and test the devices. After fabrication, the memory devices are typically tested at the wafer level. Devices that pass wafer test are then assembled and tested at the final (package) level. Devices that fail at either wafer or final test are rejected.
Because resources are expended to package and final test a memory device, it is highly desirable to identify as many defective devices as possible during wafer test so that these devices are not unnecessarily packaged. To achieve this, as many circuits as possible within the devices should be tested at the wafer level. The devices typically include some circuits that may be tested using slow-speed stimulus, and may further include other circuits (e.g., delay lock loops) that may require higher speed stimulus for testing. However, some wafer test equipments are not capable of generating the higher speed stimulus due to various reasons such as, for example, parasitic loading on test probes.
Conventionally, due in limitations of the wafer test equipment, not all circuits within the memory devices may be tested at the wafer level. If a device passes wafer test, it is subsequently packaged. The circuits in the device not tested at wafer level are then tested at the package level using equipment capable of providing the required high-speed stimulus. However, by not testing these circuits at the wafer level, there is greater likelihood of finding defects in the circuits, and thus the device, at the package level. When defects are found for the first time at the package level, additional costs has been unnecessarily incurred in packaging and processing bad devices.
As can be seen, techniques that allow high-speed circuits within an integrated circuit to be tested using slow-speed stimulus are highly desirable.
The invention provides techniques and circuits for testing high-speed circuits using slow-speed input signals. These techniques and circuits can be advantageously used for various types of integrated circuit (IC) such as a DRAM, a synchronous graphics RAM, a processor, a controller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), and others. In an aspect, various designs for a xe2x80x9cstimulusxe2x80x9d generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more slow-speed input signals. The high-speed stimulus is then used to test a high-speed circuit.
An embodiment of the invention provides a (stimulus) generator that generates an output signal (i.e., a high-speed stimulus) based on a number of (slow-speed) input signals. The generator includes first and second edge detectors coupled to a latch. Each edge detector receives a respective set of input signals and provides an intermediate signal. The latch receives the first and second intermediate signals from the first and second edge detectors and generates the output signal, which has a particular waveform pattern generated based on the active (e.g., leading) transitions in the two sets of input signals provided to the two edge detectors.
Each edge detector can be designed to include a number of pulse generators coupled to a gate. Each pulse generator receives a respective input signal and provides a pulse signal. The gate receives and combines the pulse signals from the pulse generators to generate the intermediate signal.
The input signals may be provided such that each input signal is associated with a timing offset that is different from timing offsets of other input signals. Each intermediate signal may include a sequence of pulses generated based on active transitions in the respective set of input signals. Each (leading and trailing) transition in the output signal may correspond to an active transition in one of the input signals.
Another embodiment of the invention provides a (stimulus) generator that generates an output signal (i.e., a high-speed stimulus) in response to at least one slow-speed input signal. The generator includes first, second, and third pulse generators, a delay circuit, and a latch. The delay circuit receives the output signal and provides a delayed signal. The first and second pulse generators receive the delayed signal and provide a pulse on the first and second signals, respectively, in response to leading and trailing transitions, respectively, in the delayed signal. The third pulse generator receives the input signal and provides a pulse on a third signal in response to a (e.g., leading) transition in the input signal. The generator is enabled by an enable signal and initiates operation based on the pulse on the third signal. The latch provides the output signal, which is set and reset based on the pulses in the first and second signals.
Various other aspects, embodiments, and features of the invention are described in further detail below.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.